The original set of eight 128-bit SSE registers is increased to sixteen. (These registers overlap with the x87 registers.) The 圆4 processor also provides several sets of floating-point registers:Įight 64-bit MMX registers. The instruction pointer eip and flags register have been extended to 64 bits ( rip and rflags, respectively). The high 8 bits of ax, bx, cx, and dx are still addressable as ah, bh, ch, dh but can't be used with all types of operands. Operations that output to 8-bit or 16-bit subregisters aren't zero-extended (this is compatible x86 behavior). Operations that output to a 32-bit subregister are automatically zero-extended to the entire 64-bit register. The following table specifies the assembly-language names for the lower portions of 64-bit registers. This includes registers, like esi, whose lower 8 bits weren't previously addressable. The lower 32 bits, 16 bits, and 8 bits of each register are directly addressable in operands. The new registers are named r8 through r15. For example, the 64-bit extension of eax is called rax. The 64-bit registers have names beginning with "r". X64 extends x86's 8 general-purpose registers to be 64-bit, and adds 8 new 64-bit registers. The instruction sets are almost identical. The term "圆4" includes both AMD 64 and Intel64. It provides a new 64-bit mode and a legacy 32-bit mode, which is identical to x86. The 圆4 architecture is a backwards-compatible extension of x86.
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